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________________general description the MAX192 is a low-cost, 10-bit data-acquisition system that combines an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and ultra-low power consumption. the device operates with a single +5v supply. the analog inputs are software configurable for single-ended and differential (unipolar/bipolar) operation. the 4-wire serial interface connects directly to spi, qspi, and microwire devices, without using external logic. a serial strobe output allows direct connection to tms320 family digital signal processors. the MAX192 uses either the internal clock or an external serial- interface clock to perform successive approximation a/d conversions. the serial interface can operate beyond 4mhz when the internal clock is used. the MAX192 has an internal 4.096v reference with a drift of ?0ppm typi- cal. a reference-buffer amplifier simplifies gain trim and two sub-lsbs reduce quantization errors. the MAX192 provides a hardwired shdn pin and two software-selectable power-down modes. accessing the serial interface automatically powers up the device, and the quick turn-on time allows the MAX192 to be shut down between conversions. by powering down between conversions, supply current can be cut to under 10? at reduced sampling rates. the MAX192 is available in 20-pin dip and so pack- ages, and in a shrink-small-outline package (ssop) that occupies 30% less area than an 8-pin dip. the data format provides hardware and software compati- bility with the max186/max188. for anti-aliasing filters, consult the data sheets for the max291?ax297. ________________________applications automotive pen-entry systems consumer electronics portable data logging robotics battery-powered instruments, battery management medical instruments ____________________________features ? 8-channel single-ended or 4-channel differential inputs ? single +5v operation ? low power: 1.5ma (operating) 2? (power-down) ? internal track/hold, 133khz sampling rate ? internal 4.096v reference ? 4-wire serial interface is compatible with spi, qspi, microwire, and tms320 ? 20-pin dip, so, ssop packages ? pin-compatible 12-bit upgrade (max186/max188) _______________ordering information MAX192 low-power, 8-channel, serial 10-bit adc ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 top view dip/so/ssop v dd sclk cs din sstrb dout dgnd agnd refadj vref shdn agnd ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 MAX192 ___________________pin configuration spi and qspi are trademarks of motorola corp. microwire is a trademark of national semiconductor corp. 19-0247; rev. 1; 4/97 part temp. range MAX192acpp 0? to +70? MAX192bcpp 0? to +70? MAX192acwp 0? to +70? 20 wide so 20 plastic dip 20 plastic dip pin-package MAX192bcwp 0? to +70? 20 wide so MAX192acap 0? to +70? 20 ssop MAX192bcap 0? to +70? 20 ssop ?/2 ? ?/2 inl (lsb) ? ?/2 ? MAX192aepp -40? to +85? 20 plastic dip ?/2 MAX192bepp -40? to +85? 20 plastic dip ? MAX192aewp -40? to +85? 20 wide so ?/2 MAX192bewp -40? to +85? 20 wide so ? MAX192aeap -40? to +85? 20 ssop ?/2 MAX192beap -40? to +85? 20 ssop ? MAX192amjp -55? to +125? 20 cerdip ?/2 MAX192bmjp -55? to +125? 20 cerdip ? see last page for typical operating circuit. for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 408-737-7600 ext. 3468.
MAX192 low - power , 8 - channel, serial 10 - bit adc 2 _______________________________________________________________________________________ v dd to agnd ........................................................... -0.3v to +6v agnd to dgnd .................................................... -0.3v to +0.3v ch0?h7 to agnd, dgnd ...................... -0.3v to (v dd + 0.3v) ch0?h7 total input current .......................................... 20ma vref to agnd .......................................... -0.3v to (v dd + 0.3v) refadj to agnd ...................................... -0.3v to (v dd + 0.3v) digital inputs to dgnd .............................. -0.3v to (v dd + 0.3v) digital outputs to dgnd ........................... -0.3v to (v dd + 0.3v) digital output sink current ................................................. 25ma continuous power dissipation (t a = +70 c) plastic dip (derate 11.11mw/ c above +70 c) ......... 889mw so (derate 10.00mw/ c above +70 c) ...................... 800mw ssop (derate 8.00mw/ c above +70 c) ................... 640mw cerdip (derate 11.11mw/ c above +70 c) .............. 889mw operating temperature ranges MAX192_c_p ..................................................... 0 c to +70 c MAX192_e_p .................................................. -40 c to +85 c MAX192_mjp ............................................... -55 c to +125 c storage temperature range ............................ -60 c to +150 c lead temperature (soldering, 10sec) ............................ +300 c electrical characteristics (v dd = 5v 5%, f clk = 2.0mhz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7 f capacitor at vref pin, t a = t min to t max, unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings MAX192a -3db rolloff 65khz, v in = 4.096vp-p (note 3) external reference, 4.096v MAX192b no missing codes over temperature external reference, 4.096v conditions khz 800 full-power bandwidth mhz 4.5 small-signal bandwidth db -75 channel-to-channel crosstalk db 70 sfdr spurious-free dynamic range db -70 thd total harmonic distortion (up to the 5th harmonic) db 66 sinad signal-to-noise + distortion ratio 1/2 bits 10 resolution lsb 0.1 channel-to-channel offset matching ppm/ c 0.8 gain temperature coefficient lsb 1 relative accuracy (note 2) lsb 1 dnl differential nonlinearity lsb 2 offset error lsb 2 gain error units min typ max symbol parameter internal clock 5.5 10 conversion time (note 4) t conv external clock, 2mhz, 12 clocks/conversion 6 s track/hold acquisition time t az 1.5 s aperture delay 10 ns aperture jitter <50 ps internal clock frequency 1.7 mhz dc accuracy (note 1) dynamic specifications (10khz sine-wave input, 4.096vp-p, 133ksps, 2.0mhz external clock) conversion rate
MAX192 low - power , 8 - channel, serial 10 - bit adc _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 5v 5%, f clk = 2.0mhz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7 f capacitor at vref pin, t a = t min to t max, unless otherwise noted. typical values are at t a = +25 c.) internal compensation 0ma to 0.5ma output load t a = +25 c (note 7) (note 5) on/off leakage current; v in = 0v, 5v bipolar used for data transfer only internal compensation (note 5) external compensation, 4.7 f single-ended range (unipolar only) common-mode range (any input) conditions 0 mv 2.5 load regulation (note 8) ppm/ c 30 vref tempco ma 30 vref short-circuit current v 4.066 4.096 4.126 vref output voltage pf 16 input capacitance a 0.01 1 multiplexer leakage current v -v ref +v ref -2 2 analog input voltage (note 6) 0 v ref 0 v ref 0 v dd mhz 10 external clock frequency 0.1 0.4 0.1 2.0 units min typ max symbol parameter capacitive bypass at vref external compensation 4.7 f internal compensation 0.01 capacitive bypass at refadj external compensation 0.01 f refadj adjustment range 1.5 % input voltage range 2.5 v dd + 50mv v input current 200 350 a input resistance 12 20 k shutdown vref input current 1.5 10 a buffer disable threshold refadj v dd - 50mv v unipolar differential range internal compensation mode 0 capacitive bypass at vref external compensation mode 4.7 f reference-buffer gain 1.678 v/v refadj input current 50 a analog input internal reference (reference buffer enabled) external reference at vref (buffer disabled, vref = 4.096v) external reference at refadj
note 1: tested at v dd = 5.0v; single-ended, unipolar. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 3: grounded on-channel; sine wave applied to all off channels. note 4: conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle. note 5: guaranteed by design. not subject to production testing. note 6: the common-mode range for the analog inputs is from agnd to v dd . note 7: sample tested to 0.1% aql. note 8: external load should not change during conversion for specified accuracy. note 9: measured at v supply + 5% and v supply - 5% only. MAX192 low - power , 8 - channel, serial 10 - bit adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 5v 5%, f clk = 2.0mhz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7 f capacitor at vref pin, t a = t min to t max, unless otherwise noted. typical values are at t a = +25 c.) i sink = 16ma i sink = 5ma shdn = open shdn = open shdn = 0v shdn = v dd (note 5) v in = 0v or v dd conditions v 0.3 v ol output voltage low 0.4 na -100 100 shdn max allowed leakage, mid input v 2.75 v flt shdn voltage, floating v 1.5 v dd - 1.5 v im shdn input mid voltage a -4.0 i inl shdn input current, low a 4.0 i inh shdn input current, high v 0.5 v inl shdn input low voltage v v dd - 0.5 v inh shdn input high voltage pf 15 c in din , sclk, cs input capacitance a 1 i in din, sclk, cs input leakage v 0.15 v hyst din, sclk, cs input hysteresis v 0.8 v inl din , sclk, cs input low voltage v 2.4 v inh din , sclk, cs input high voltage units min typ max symbol parameter output voltage high v oh i source = 1ma 4 v three-state leakage current i l cs = 5v 10 a three-state leakage capacitance c out cs = 5v (note 5) 15 pf positive supply voltage v dd 5 5% v operating mode 1.5 2.5 ma fast power-down 30 70 positive supply current i dd full power-down 2 10 a positive supply rejection (note 9) psr v dd = 5v 5%; external reference, 4.096v; full-scale input 0.06 0.5 mv external reference at refadj digital inputs (din, sclk, c s , s h d n ) digital outputs (dout, sstrb) power requirements
note 5: guaranteed by design. not subject to production testing. MAX192 low - power , 8 - channel, serial 10 - bit adc _______________________________________________________________________________________ 5 timing characteristics (v dd = 5v 5%, t a = t min to t max , unless otherwise noted.) c load = 100pf external clock mode only, c load = 100pf c load = 100pf c load = 100pf c load = 100pf external clock mode only, c load = 100pf conditions ns 200 t str cs rise to sstrb output disable (note 5) cs fall to sstrb output enable (note 5) ns 200 t sdv ns 0 t dh din to sclk hold ns 100 t ds s 1.5 t az acquisition time din to sclk setup ns 200 t sstrb sclk fall to sstrb ns 200 t cl sclk pulse width low ns 200 t ch sclk pulse width high ns 0 t csh cs to sclk rise hold ns 20 150 t do ns 100 t dv ns 100 t tr sclk fall to output data valid ns 100 t css cs to sclk rise setup units min typ max symbol parameter sstrb rise to sclk rise (note 5) t sck internal clock mode only 0 ns cs rise to output disable cs fall to output enable __________________________________________ t ypical operating characteristics 0.16 0 -60 -20 60 140 channel-to-channel offset matching vs. temperature 0.02 0.12 temperature (?) offset matching (lsbs) 20 100 0.10 0.04 -40 0 40 80 120 0.14 0.08 0.06 0.30 -0.05 -60 140 power-supply rejection vs. temperature 0 0.25 temperature (?) psr (lsbs) 60 0.10 0.05 -40 20 100 0.15 0.20 -20 0 40 80 120 v dd = +5v ?% 2.456 internal reference voltage vs. temperature 2.452 2.455 temperature (?) vrefadj (v) 2.454 2.453 -40 -20 0 20 40 60 80 100 120 -60 140
MAX192 low-power , 8-channel, serial 10-bit adcs 6 ________________________________________________________________________________________________ +5v 3k c load dgnd dout c load dgnd 3k dout a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol +3v 3k c load dgnd dout c load dgnd 3k dout a) v oh to high-z b) v ol to high-z figure 1. load circuits for enable time figure 2. load circuits for disabled time pin description pin name function 1? ch0?h7 sampling analog inputs 9, 13 agnd analog ground. also in- input for single-enabled conversions. connect both agnd pins to analog ground. 10 shdn three-level shutdown input. pulling shdn low shuts the MAX192 down to 10 a (max) supply cur - rent, otherwise the MAX192 is fully operational. pulling shdn high puts the reference-buffer amplifi - er in internal compensation mode. letting shdn float puts the reference-buffer amplifier in external compensation mode. 11 vref reference voltage for analog-to-digital conversion. also, output of the reference buffer amplifier. add a 4.7 f capacitor to ground when using external compensation mode. also functions as an input when used with a precision external reference. 12 refadj reference-buffer amplifier input. to disable the reference-buffer amplifier, tie refadj to v dd . 14 dgnd digital ground 15 dout serial data output. data is clocked out at the falling edge of sclk. high impedance when cs is high. 16 sstrb serial strobe output. in internal clock mode, sstrb goes low when the MAX192 begins the a/d conversion and goes high when the conversion is done. in external clock mode, sstrb pulses high for one clock period before the msb decision. sstrb is high impedance when cs is high (external mode). 17 din serial data input. data is clocked in at the rising edge of sclk. 18 cs active-low chip select. data will not be clocked into din unless cs is low. when cs is high, dout is high impedance. 19 sclk serial clock input. clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed. (duty cycle must be 40% to 60% in external clock mode.) 20 v dd positive supply voltage, +5v 5%
MAX192 low - power , 8 - channel, serial 10 - bit adc _______________________________________________________________________________________ 7 input shift register control logic int clock output shift register +2.46v reference t/h analog input mux sar adc in dout sstrb v dd dgnd sclk din ch0 ch1 ch3 ch2 ch7 ch6 ch5 ch4 agnd refadj vref out ref clock +4.096v 20k ? 1.65 1 2 3 4 5 6 7 8 10 11 12 13 15 16 17 18 19 cs shdn a 20 14 agnd 9 MAX192 figure 3. block diagram detailed description the MAX192 uses a successive - approximation conver - sion technique and input track/hold (t/h) circuitry to convert an analog signal to a 10 - bit digital output. a flexible serial interface provides easy interface to microprocessors. no external hold capacitors are required. figure 3 shows the block diagram for the MAX192. pseudo - differential input the sampling architecture of the adc? analog com - parator is illustrated in the equivalent input circuit (figure 4). in single - ended mode, in+ is internally switched to ch0?h7 and in - is switched to agnd. in differential mode, in+ and in - are selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. refer to tables 1 and 2 to configure the channels. in differential mode, in - and in+ are internally switched to either one of the analog inputs. this configuration is pseudo - differential to the effect that only the signal at in+ is sampled. the return side (in - ) must remain sta - ble within 0.5lsb ( 0.1lsb for best results) with respect to agnd during a conversion. accomplish this by connecting a 0.1 f capacitor from ain - (the select - ed analog input, respectively) to agnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans three sclk cycles and ends on the falling sclk edge after the last bit of the input control word has been entered. at the end of the acqui - sition interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplex - er switching c hold from the positive input (in+) to the negative input (in - ). in single - ended mode, in - is simply agnd. this unbalances node zero at the input of the comparator. the capacitive dac adjusts during the remainder of the conversion cycle to restore its node zero to 0v within the limits of its resolution. this action is equivalent to transferring a charge of 16pf x (v in + - v in - ) from c hold to the binary - weighted capacitive dac, which in turn forms a digital represen - tation of the analog input signal. ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd c switch track t/h switch 10k r s c hold hold capacitive dac vref zero comparator + 16pf single-ended mode: in+ = cho-ch7, in- = agnd. differential mode (bipolar): in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5 , ch6/ch7. at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. input mux figure 4. equivalent input circuit
MAX192 track/hold the t/h enters its tracking mode on the falling clock edge after the fifth bit of the 8 - bit control word has been shifted in. the t/h enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. if the converter is set up for single - ended inputs, in - is connected to agnd, and the converter samples the ??input. if the converter is set up for differ - ential inputs, in - connects to the - ?input, and the differ - ence of ? in+ - in - ? is sampled. at the end of the conver - sion, the positive input connects back to in+, and c hold charges to the input signal. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisi - tion time lengthens and more time must be allowed between conversions. acquisition time is calculated by: t az = 9 (r s + r in ) 16pf where r in = 5k , r s = the source impedance of the input signal, and taz is never less than 1.5 s. note that source impedances below 5kw do not significantly affect the ac performance of the adc. higher source imped - ances can be used if an input capacitor is connected to the analog inputs, as shown in figure 5. note that the input capacitor forms an rc filter with the input source impedance, limiting the adc? signal bandwidth. input bandwidth the adc? input tracking circuitry has a 4.5mhz small - signal bandwidth, so it is possible to digitize high - speed transient events and measure periodic sig - nals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high - frequency signals being aliased into the frequency band of interest, anti - alias filtering is recommended. see the data sheets for the max291?ax297 filters. analog input range and input protection internal protection diodes, which clamp the analog input to v dd and agnd, allow the channel input pins to swing from agnd - 0.3v to v dd + 0.3v without dam - age. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv, or be lower than agnd by 50mv. if the analog input exceeds 50mv beyond the sup - plies, do not forward bias the protection diodes of off channels over 2ma. the MAX192 can be configured for differential (unipolar or bipolar) or single-ended (unipolar only) inputs, as selected by bits 2 and 3 of the control byte (table 3). in the single-ended mode, set the uni/bip bit to unipolar. in this mode, analog inputs are internally referenced to agnd, with a full-scale input range from 0v to v ref . in differential mode, both unipolar and bipolar settings can be used. choosing unipolar mode sets the differen - tial input range at 0v to v ref . the output code is invalid (code zero) when a negative differential input voltage is applied. bipolar mode sets the differential input range to v ref / 2. note that in this differential mode, the com - mon-mode input range includes both supply rails. refer to tables 4a and 4b for input voltage ranges. quick look to evaluate the analog performance of the MAX192 quickly, use figure 5? circuit. the MAX192 requires a control byte to be written to din before each conversion. tying din to +5v feeds in control bytes of low - power , 8 - channel, serial 10 - bit adc 8 _______________________________________________________________________________________ table 1. channel selection in single - ended mode (sgl/ dif = 1) sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd 0 0 0 + 1 0 0 + 0 0 1 + 1 0 1 + 0 1 0 + 1 1 0 + 0 1 1 + 1 1 1 +
MAX192 low - power , 8 - channel, serial 10 - bit adc _______________________________________________________________________________________ 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 bit name description 7(msb) start the first logic 1 ?bit after cs goes low defines the beginning of the control byte. 6 sel2 these three bits select which of the eight channels are used for the conversion. 5 sel1 see tables 1 and 2. 4 sel0 3 uni/ bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, an analog input signal from 0v to vref can be converted; in differential bipolar mode, the differential signal can range from - vref / 2 to +vref / 2. select differential operation if bipolar mode is used. 2 sgl/ dif 1 = single ended, 0 = differential. selects single - ended or differential conversions. in single - ended mode, input signal voltages are referred to agnd. in differential mode, the voltage difference between two channels is measured. select unipolar operation if single-ended mode is used. see tables 1 and 2. 1 pd1 selects clock and power - down modes. 0(lsb) pd0 pd1 pd0 mode 0 0 full power - down (i q = 2 a) 0 1 fast power - down (i q = 30 a) 1 0 internal clock mode 1 1 external clock mode table 3. control-byte format table 2. channel selection in differential mode (sgl/ dif = 0) sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 0 0 0 + 0 0 1 + 0 1 0 + 0 1 1 + 1 0 0 + 1 0 1 + 1 1 0 + 1 1 1 +
MAX192 low - power , 8 - channel, serial 10 - bit adc 10 ______________________________________________________________________________________ $ff (hex), which trigger single - ended conversions on ch7 in external clock mode without powering down between conversions. in external clock mode, the sstrb output pulses high for one clock period before the most significant bit of the conversion result comes out of dout. varying the analog input to ch7 should alter the sequence of bits from dout. a total of 15 clock cycles is required per conversion. all transitions of the sstrb and dout outputs occur on the falling edge of sclk. how to start a conversion a conversion is started on the MAX192 by clocking a control byte into din. each rising edge on sclk, with cs low, clocks a bit from din into the MAX192? internal shift register. after cs falls, the first arriving logic ??bit defines the msb of the control byte. until this first ?tart?bit arrives, any number of logic ??bits can be clocked into din with no effect. table 3 shows the control - byte format. the MAX192 is compatible with microwire, spi, and qspi devices. for spi, select the correct clock polarity and sampling edge in the spi control registers: set cpol = 0 and cpha = 0. microwire and spi both transmit a byte and receive a byte at the same time. using the typical operating circuit , the simplest soft - ware interface requires only three 8 - bit transfers to per - form a conversion (one 8 - bit transfer to configure the adc, and two more 8 - bit transfers to clock out the 12 - bit conversion result). example: simple software interface make sure the cpu? serial interface runs in master mode so the cpu generates the serial clock. choose a clock frequency from 100khz to 2mhz. 1) set up the control byte for external clock mode, call it tb1. tb1 should be of the format: 1xxxxx11 binary, where the xs denote the par - ticular channel and conversion - mode selected. 2) use a general - purpose i/o line on the cpu to pull cs on the MAX192 low. 3) transmit tb1 and simultaneously receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and simultaneously receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and simultaneously receive byte rb3. 6) pull cs on the MAX192 high. figure 6 shows the timing for this sequence. bytes rb2 and rb3 will contain the result of the conversion padded with one leading zero, two sub-lsb bits, and three trailing zeros. the total conversion time is a func - tion of the serial clock frequency and the amount of dead time between 8 - bit transfers. make sure that the total conversion time does not exceed 120 s, to avoid excessive t/h droop. digital output in unipolar input mode, the output is straight binary (figure 15). for bipolar inputs in differential mode, the output is twos - complement (figure 16). data is clocked out at the falling edge of sclk in msb - first format. internal and external clock modes the MAX192 may use either an external serial clock or the internal clock to perform the successive - approxima - tion conversion. in both clock modes, the external clock shifts data in and out of the MAX192. the t/h acquires the input signal as the last three bits of the control byte are clocked into din. bits pd1 and pd0 of the control byte program the clock mode. figures 7 through 10 show the timing characteristics common to both modes. reference zero scale full scale internal reference 0v +4.096v external reference 0v v ref at refadj at vref 0v v refadj (1.678) table 4a. unipolar full scale and zero scale table 4b. differential bipolar full scale, zero scale, and negative full scale reference negative full scale full scale internal reference -4.096v / 2 +4.096v / 2 external referenc e -1/2v refadj (1.678) +1/2v ref at refadj 0.at vref -1/2v ref +1/2v refadj (1.678) zero scale 0v 0v 0v
external clock in external clock mode, the external clock not only shifts data in and out, it also drives the analog - to - digital conversion steps. sstrb pulses high for one clock period after the last bit of the control byte. successive - approximation bit decisions are made and appear at dout on each of the next 12 sclk falling edges (see figure 6). the first 10 bits are the true data bits, and the last two are sub-lsb bits. sstrb and dout go into a high - impedance state when cs goes high; after the next cs falling edge, sstrb will output a logic low. figure 8 shows the sstrb timing in external clock mode. the conversion must complete in some minimum time, or else droop on the sample - and - hold capacitors may degrade conversion results. use internal clock mode if the clock period exceeds 10 s, or if serial - clock interruptions could cause the conversion interval to exceed 120 s. internal clock in internal clock mode, the MAX192 generates its own conversion clock internally. this frees the microproces - sor from the burden of running the sar conversion clock, and allows the conversion results to be read back at the processor? convenience, at any clock rate from zero to typically 10mhz. sstrb goes low at the start of the conversion and then goes high when the conversion is complete. sstrb will be low for a maxi - mum of 10 s, during which time sclk should remain low for best noise performance. an internal register stores data when the conversion is in progress. sclk clocks the data out at this register at any time after the conversion is complete. after sstrb goes high, the next falling clock edge will produce the msb of the conversion at dout, followed by the remaining bits in msb - first format (figure 9). cs does not need to be held low once a conversion is started. MAX192 low - power , 8 - channel, serial 10 - bit adc ______________________________________________________________________________________ 11 0.1 m f v dd dgnd agnd agnd cs sclk din dout sstrb shdn +5v n.c. 0.01 m f ch7 refadj vref c2 0.01 m f +2.5v reference c1 4.7 m f 0v to 4.096v analog input +2.5v ** oscilloscope ch1 ch2 ch3 ch4 * full-scale analog input, conversion result = $fff (hex) **optional. a potentiometer may be used in place of the reference for test pur poses. MAX192 +5v 2mhz oscillator sclk sstrb dout* figure 5. quick-look circuit
MAX192 low - power , 8 - channel, serial 10 - bit adc 12 ______________________________________________________________________________________ sstrb cs sclk din dout 1 4 8 12 16 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b9 msb b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb s1 so acquisition 1.5? (clk = 2mhz) idle filled with zeros idle conversion t acq a/d state rb1 rb1 rb2 rb3 rb2 rb3 cs sclk din dout t csh t css t cl t ds t dh t dv t ch t do t tr t csh figure 6. 24-bit external clock mode conversion timing (spi, qspi and microwire compatible) figure 7. detailed serial-interface timing pulling cs high prevents data from being clocked into the MAX192 and three - states dout, but it does not adversely affect an internal clock - mode conversion already in progress. when internal clock mode is selected, sstrb does not go into a high - impedance state when cs goes high. figure 10 shows the sstrb timing in internal clock mode. in internal clock mode, data can be shifted in and out of the MAX192 at clock rates exceeding 4.0mhz, provided that the minimum acquisition time, t az , is kept above 1.5 s. data framing the falling edge of cs does not start a conversion on the MAX192. the first logic high clocked into din is inter - preted as a start bit and defines the first bit of the control byte. a conversion starts on the falling edge of sclk, after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as: the first high bit clocked into din with cs low any - time the converter is idle, e.g. after v dd is applied. or the first high bit clocked into din after bit 3 of a conversion in progress is clocked onto the dout pin. if a falling edge on cs forces a start bit before bit 3 (b3) becomes available, then the current conversion will be terminated and a new one started. thus, the fastest the MAX192 can run is 15 clocks per conver - sion. figure 11a shows the serial - interface timing nec - essary to perform a conversion every 15 sclk cycles in external clock mode. if cs is low and sclk is contin - uous, guarantee a start bit by first clocking in 16 zeros.
most microcontrollers require that conversions occur in multiples of 8 sclk clocks; 16 clocks per conversion will typically be the fastest that a microcontroller can drive the MAX192. figure 11b shows the serial - inter - face timing necessary to perform a conversion every 16 sclk cycles in external clock mode. __________ applications infor mation power - on reset when power is first applied and if shdn is not pulled low, internal power - on reset circuitry will activate the MAX192 in internal clock mode, ready to convert with sstrb = high. after the power supplies have been sta - bilized, the internal reset time is 100 s and no conver - sions should be performed during this phase. sstrb is high on power - up and, if cs is low, the first logical 1 on din will be interpreted as a start bit. until a conversion takes place, dout will shift out zeros. reference - buffer compensation in addition to its shutdown function, the shdn pin also selects internal or external compensation. the compen - sation affects both power - up time and maximum conver - sion speed. compensated or not, the minimum clock rate is 100khz due to droop on the sample - and - hold. to select external compensation, float shdn . see the typical operating circuit , which uses a 4.7 f capacitor at vref. a value of 4.7 f or greater ensures stability and allows operation of the converter at the full clock speed of 2mhz. external compensation increases power - up time (see the choosing power - down mode section, and table 5). internal compensation requires no external capacitor at vref, and is selected by pulling shdn high. internal compensation allows for shortest power - up times, but is only available using an external clock and reduces the maximum clock rate to 400khz. MAX192 low - power , 8 - channel, serial 10 - bit adc ______________________________________________________________________________________ 13 t sdv t sstrb pd0 clocked in t str sstrb sclk cs t sstrb sstrb cs sclk din dout 1 4 8 12 18 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b9 msb b8 b7 b0 lsb s1 s0 acquisition 1.5? (clk = 2mhz) idle filled with zeros idle conversion 10? max a/d state 2 3 5 6 7 9 10 11 19 21 22 23 t conv figure 8. external clock mode sstrb detailed timing figure 9. internal clock mode timing
MAX192 low - power , 8 - channel, serial 10 - bit adc 14 ______________________________________________________________________________________ pd0 clock in t sstrb t csh t conv t sck sstrb sclk t css note: for best noise performance, keep sclk low during conversion. cs sclk din dout cs s control byte 0 control byte 1 s conversion result 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 s1 s0 conversion result 1 sstrb b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 s1 s0 control byte 2 s 1 8 1 8 1 cs sclk din dout s control byte 0 control byte 1 s conversion result 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 s1 s0 b9 b8 b7 b6 conversion result 1 figure 10. internal clock mode sstrb detailed timing figure 11a. external clock mode, 15 clocks/conversion timing figure 11b. external clock mode, 16 clocks/conversion timing
power - down choosing power - down mode you can save power by placing the converter in a low - current shutdown state between conversions. select full power - down or fast power - down mode via bits 1 and 0 of the din control byte with shdn either high or floating (see tables 3 and 6). pull shdn low a t any time to shut down the converter completely. shdn overrides bits 1 and 0 of din word (see table 7). full power - down mode turns off all chip functions that draw quiescent current, typically reducing i dd to 2 a. fast power - down mode turns off all circuitry except the bandgap reference. with the fast power - down mode, the supply current is 30 a. power - up time can be shortened to 5 s in internal compensation mode. in both software shutdown modes, the serial interface remains operational, however, the adc will not convert. table 5 illustrates how the choice of reference - buffer compensation and power - down mode affects both power - up delay and maximum sample rate. in external compensation mode, the power - up time is 20ms with a 4.7 f compensation capacitor when the capacitor is fully discharged. in fast power - down, you can eliminate start - up time by using low - leakage capaci - MAX192 low - power , 8 - channel, serial 10 - bit adc ______________________________________________________________________________________ 15 powered up full power- down powered up powered up data valid (10 + 2 data bits) data valid (10 + 2 data bits) data invalid valid external external internal s x x x x x 1 1 s 0 1 x x x x x x x x x x s 1 1 fast power-down mode dout din clock mode shdn sets external clock mode sets external clock mode sets fast power-down mode figure 12a. timing diagram power-down modes, external clock full power-down powered up powered up data valid data valid internal clock mode s x x x x x 1 0 s 0 0 x x x x x s mode dout din clock mode sets internal clock mode sets full power-down conversion conversion sstrb figure 12b. timing diagram power-down modes, internal clock
MAX192 low - power , 8 - channel, serial 10 - bit adc 16 ______________________________________________________________________________________ reference reference - vref power - power-up maximum buffer buffer capacitor down delay sampling compensation ( f) mode (sec) rate (ksps) mode enabled internal fast 5 26 enabled internal full 300 26 enabled external 4.7 fast see figure 14c 133 enabled external 4.7 full see figure 14c 133 disabled fast 2 133 disabled full 2 133 table 5. worst-case power-up delay times pd1 pd0 device mode 1 1 external clock mode 1 0 internal clock mode 0 1 fast power - down mode 0 0 full power - down mode s s h h d d n n device reference - buffer state mode compensation 1 enabled internal compensation floating enabled external compensation 0 full power-down n/a tors that will not discharge more than 1/2lsb while shut down. in shutdown, the capacitor has to supply the cur - rent into the reference (1.5 a typ) and the transient cur - rents at power - up. figures 12a and 12b illustrate the various power - down sequences in both external and internal clock modes. software power - down software power - down is activated using bits pd1 and pd0 of the control byte. as shown in table 6, pd1 and pd0 also specify the clock mode. when software shut - down is asserted, the adc will continue to operate in the last specified clock mode until the conversion is complete. then the adc powers down into a low quies - cent - current state. in internal clock mode, the interface remains active and conversion results may be clocked out while the MAX192 has already entered a software power - down. the first logical 1 on din will be interpreted as a start bit, and powers up the MAX192. following the start bit, the data input word or control byte also determines clock and power - down modes. for example, if the din word contains pd1 = 1, then the chip will remain pow - ered up. if pd1 = 0, a power - down will resume after one conversion. hardware power - down t he shdn pin places the converter into the full power - down mode. unlike with the software shutdown modes, conversion is not completed. it stops coinci - dentally with shdn being brought low. there is no power - up delay if an external reference is used and is not shut down. the shdn pin also selects internal or external reference compensation (see table 7). power - down sequencing the MAX192 auto power - down modes can save con - siderable power when operating at less than maximum sample rates. the following discussion illustrates the various power - down sequences. lowest power at up to 500 conversions/channel/second the following examples illustrate two different power - down sequences. other combinations of clock rates, compensation modes, and power - down modes may give lowest power consumption in other applica - tions. figure 14a depicts the MAX192 power consumption for one or eight channel conversions utilizing full power - down mode and internal reference compensa - tion. a 0.01 f bypass capacitor at refadj forms an table 7. hard - wired shutdown and compensation mode table 6. software shutdown and clock mode
MAX192 low - power , 8 - channel, serial 10 - bit adc ______________________________________________________________________________________ 17 1 0 0 din refadj vref 2.5v 0v 4v 0v 1 0 1 1 1 1 1 0 0 1 0 1 fullpd fastpd nopd fullpd fastpd 2ms wait complete conversion sequence t buffen ? 15 m s t = rc = 20k w x c refadj (zeros) ch1 ch7 (zeros) figure 13. fullpd/fastpd power-up sequence rc filter with the internal 20k reference resistor with a 0.2ms time constant. to achieve full 10 - bit accuracy, 10 time constants or 2ms are required after power - up. waiting 2ms in fastpd mode instead of full power-up will reduce the power consumption by a factor of 10 or more. this is achieved by using the sequence shown in figure 13. lowest power at higher throughputs figure 14b shows the power consumption with external - reference compensation in fast power - down, with one and eight channels converted. the external 4.7 f compensation requires a 50 s wait after power - up, accomplished by 75 idle clocks after a dummy conversion. this circuit combines fast multi - channel conversion with lowest power consump - tion possible. full power - down mode may provide increased power savings in applications where the 1000 1 0 100 300 500 full power-down 10 100 MAX192-14a conversions per channel per second 200 400 2ms fastpd wait 400khz external clock internal compensation 8 channels 1 channel avg. supply current ( m a) 10,000 10 0 fast power-down 100 1000 conversions per channel per second 8 channels 1 channel 4k 8k 12k 16k 2mhz external clock external compensation 50? wait avg. supply current ( m a) MAX192-14b 3.0 2.5 2.0 1.5 1.0 0.5 0 0.0001 0.001 0.01 0.1 1 10 time in shutdown (sec) power-up delay (ms) figure 14a. supply current vs. sample rate/second, fullpd, 400khz clock figure 14b. supply current vs. sample rate/second, fastpd, 2mhz clock figure 14c. typical power-up delay vs. time in shutdown
MAX192 MAX192 is inactive for long periods of time, but where intermittent bursts of high - speed conversions are required. external and internal references the MAX192 can be used with an internal or external reference. diode d1 shown in the typical operating circuit ensures correct start - up. any standard signal diode can be used. an external reference can either be connected directly at the vref terminal or at the refadj pin. the MAX192? internally trimmed 2.46v reference is buffered with a gain of 1.678 to scale an external 2.5v reference at refadj to 4.096v at vref. internal reference the full - scale range of the MAX192 with internal reference is 4.096v with unipolar inputs, and 2.048v with differen - tial bipolar inputs. the internal reference voltage is adjustable to 1.5% with the reference - adjust circuit of figure 17. external reference a n external reference can be placed at either the input (refadj) or the output (vref) of the internal buffer amplifier. the refadj input impedance is typically 20k . at vref, the input impedance is a minimum of 12k for dc currents. during conversion, an external reference at vref must be able to deliver up to 350 a dc load current and have an output impedance of 10 or less. if the reference has higher output impedance or is noisy , bypass it close to the vref pin with a 4.7 f capacitor. using the buffered refadj input avoids external buffering of the reference. to use the direct vref input, disable the internal buffer by tying refadj to v dd . transfer function and gain adjust figure 15 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 16 shows the differ - ential bipolar input/output transfer function. code transitions occur halfway between successive integer lsb values. output coding is binary with 1lsb = 4.00mv (4.096v / 1024) for unipolar operation and 1lsb = 4.00mv [(4.096v / 2 - - 4.096v / 2)/1024] for bipolar operation. figure 17, the reference - adjust circuit, shows how to adjust the adc gain in applications that use the internal reference. the circuit provides 1.5% ( 15lsbs) of gain adjustment range. low - power , 8 - channel, serial 10 - bit adc 18 ______________________________________________________________________________________ output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 1 2 3 0 fs fs - 3/2lsb fs = +4.096v 1lsb = fs 1024 input voltage (lsbs) 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 -fs 0v differential input voltage (lsbs) +fs - 1lsb fs = +4.096 2 1lsb = +4.096 1024 output code figure 15. unipolar transfer function, 4.096v = full scale figure 16. differential bipolar transfer function, 4.096v / 2 = full scale
layout, grounding, bypassing for best performance, use printed circuit boards. wire - wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digi - tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 18 shows the recommended system ground connections. a single - point analog ground (?tar ground point) should be established at agnd, sepa - rate from the logic ground. all other analog grounds and dgnd should be connected to this ground. no other digital system ground should be connected to this single - point analog ground. the ground return to the power supply for this ground should be low imped - ance and as short as possible for noise - free operation. high - frequency noise in the v dd power supply may affect the high - speed comparator in the adc. bypass these supplies to the single - point analog ground with 0.1 f and 4.7 f bypass capacitors close to the MAX192 . minimize capacitor lead lengths for best sup - ply - noise rejection. if the +5v power supply is very noisy, a 10 resistor can be connected as a low pas s filter, as shown in figure 18. high - speed digital interfacing the MAX192 can interface with qspi at high through - put rates using the circuit in figure 19. this qspi circuit can be programmed to do a conversion on each of the eight channels. the result is stored in memory without taxing the cpu since qspi incorporates its own micro - sequencer. figure 20 details the code that sets up qspi for autonomous operation. in external clock mode, the MAX192 performs a single - ended, unipolar conversion on each of the eight analog input channels. figure 21 shows the timing associated with the assembly code of figure 20. the first byte clocked into the MAX192 is the control byte, which triggers the first conversion on ch0. the last two bytes clocked into the MAX192 are all zero, and clock out the results of the ch7 conversion. MAX192 low - power , 8 - channel, serial 10 - bit adc ______________________________________________________________________________________ 19 +5v 510k 100k 24k 0.01 m f 12 refadj MAX192 figure 17. reference-adjust circuit +5v gnd supplies dgnd +5v dgnd agnd v dd digital circuitry MAX192 r* = 10 w * optional figure 18. power-supply grounding connection
MAX192 low - power , 8 - channel, serial 10 - bit adc 20 ______________________________________________________________________________________ 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 MAX192 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd shdn v dd sclk cs din sstrb dout dgnd agnd refadj vref v ddi , v dde , v ddsyn , v stby sck pcs0 mosi miso * clock connections not shown v ssi v sse mc68hc16 0.1 m f 4.7 m f 0.01 m f 0.1 m f 4.7 m f analog inputs +5v + figure 19. MAX192 qspi connection tms320 to MAX192 interface figure 22 shows an application circuit to interface the MAX192 to the tms320 in external clock mode. the timing diagram for this interface circuit is shown in figure 23. use the following steps to initiate a conversion in the MAX192 and to read the results: 1) the tms320 should be configured with clkx (transmit clock) as an active - high output clock and clkr (tms320 receive clock) as an active - high input clock. clkx and clkr of the tms320 are tied together with the sclk input of the MAX192. 2) the MAX192 cs is driven low by the xf_ i/o port of the tms320 to enable data to be clocked into din of the MAX192. 3) an 8 - bit word (1xxxxx11) should be written to the MAX192 to initiate a conversion and place the device into external clock mode. refer to table 3 to select the proper xxxxx bit values for your spe - cific application. 4) the sstrb output of the MAX192 is monitored via the fsr input of the tms320. a falling edge on the sstrb output indicates that the conversion is in progress and data is ready to be received from the MAX192. 5) the tms320 reads in one data bit on each of the next 16 rising edges of sclk. these data bits rep - resent the 10 - bit conversion result and two sub- lsbs, followed by four trailing bits, which should be ignored. 6) pull cs high to disable the MAX192 until the next conversion is initiated.
MAX192 low - power , 8 - channel, serial 10 - bit adc ______________________________________________________________________________________ 21 * description : * this is a shell program for using a stand - alone 68hc16 without any external memory. the internal 1k ram * is put into bank $0f to maintain 68hc11 code compatibility. this program was written with software * provided in the motorola 68hc16 evaluation kit. * * roger j.a. chen, applications engineer * maxim integrated products * november 20, 1992 * ******************************************************************************************************************************* *********************** include ?quates.asm? ;equates for common reg addrs include ?rg00000.asm? ;initialize reset vector include ?rg00008.asm? ;initialize interrupt vectors org $0200 ;start program after interrupt vectors include ?nitsys.asm ;set ek=f,xk=0,yk=0,zk=0 ;set sys clock at 16.78 mhz, cop off include ?nitram.asm? ;turn on internal sram at $10000 ;set stack (sk=1, sp=03fe) main: jsr initqspi mainloop: jsr read192 wait: ldaa spsr anda #$80 beq wait ;wait for qspi to finish bra mainloop endprogram: initqspi: ;this routine sets up the qspi microsequencer to operate on its own. ;the sequencer will read all eight channels of a MAX192 each time ;it is triggered. the a/d converter results will be left in the ;receive data ram. each 16 bit receive data ram location will ;have a leading zero, 10 + 2 bits of conversion result and three zeros. ; ;receive ram bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ;a/d result 0 msb lsb 0 0 0 ***** initialize the qspi registers ****** psha pshb ldaa #%01111000 staa qpdr ;idle state for pcs0 - 3 = high ldaa #%01111011 staa qpar ;assign port d to be qspi ldaa #%01111110 staa qddr ;only miso is an input ldd #$8008 std spcr0 ;master mode,16 bits/transfer, ;cpol=cpha=0,1mhz ser clock ldd #$0000 std spcr1 ;set delay between pcs0 and sck, ;set delay between transfers figure 20. MAX192 assembly-code listing
MAX192 low - power , 8 - channel, serial 10 - bit adc 22 ______________________________________________________________________________________ ldd #$0800 std spcr2 ;set endqp to $8 for 9 transfers ***** initialize qspi command ram ***** ldaa #$80 ;cont=1,bitse=0,dt=0,dsck=0,pcs0=active staa $fd40 ;store first byte in command ram ldaa #$c0 ;cont=1,bitse=1,dt=0,dsck=0,pcs0=active staa $fd41 staa $fd42 staa $fd43 staa $fd44 staa $fd45 staa $fd46 staa $fd47 ldaa #$40 ;cont=0,bitse=1,dt=0,dsck=0,pcs0=active staa $fd48 ***** initialize qspi transmit ram ***** ldd #$008f std $fd20 ldd #$00cf std $fd22 ldd #$009f std $fd24 ldd #$00df std $fd26 ldd #$00af std $fd28 ldd #$00ef std $fd2a ldd #$00bf std $fd2c ldd #$00ff std $fd2e ldd #$0000 std $fd30 pulb pula rts read192: ;this routine triggers the qspi microsequencer to autonomously ;trigger conversions on all 8 channels of the MAX192. each ;conversion result is stored in the receive data ram. psha ldaa #$80 oraa spcr1 staa spcr1 ;just set spe pula rts ***** interrupts/exceptions ***** bdm: bgnd ;exception vectors point here ;and put the user in background debug mode figure 20. MAX192 assembly-code listing (continued)
MAX192 low - power , 8 - channel, serial 10 - bit adc ______________________________________________________________________________________ 23 cs sclk sstrb din figure 21. qspi assembly-code timing xf clkx clkr dx dr fsr cs sclk din dout sstrb tms320 MAX192 figure 22. MAX192 to tms320 serial interface cs sclk din sstrb dout start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0 msb b10 s1 s0 high impedance high impedance figure 23. tms320 serial-interface timing diagram
MAX192 low - power , 8 - channel, serial 10 - bit adc t ypical operating cir cuit chip infor mation v dd i/o sck (sk)* mosi (so) miso (si) v ss shdn sstrb dout din sclk cs agnd agnd dgnd v dd refadj ch7 c3 0.1 m f c4 0.1 m f ch0 +5v c2 0.01 m f 0v to 4.096v analog inputs MAX192 cpu c1 4.7 m f vref transistor count: 2278 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1997 maxim integrated products printed usa is a registered trademark of maxim integrated products. ssop.eps package infor mation

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